SAP and mSAP for PCBs: How Fine Traces Are Made, and What Has Changed by 2026

Mitsui Mining & Smelting's process comparison uses approximately 1–3 μm of base copper for mSAP and a 0.5–1 μm seed layer for SAP as examples. GS Swiss PCB describes capabilities of approximately 20–60 μm for mSAP and 10 μm or finer for SAP. These are technical descriptions from different suppliers and products, not universal industry boundaries. Materials, copper thickness, layer count, and acceptable yield all affect actual production specifications. [1][2]

For a SAP build-up layer containing microvias, a simplified sequence is: laminate the insulating layer → laser-drill and desmear → activate and form the seed layer → laminate dry film, expose, and develop → pattern-plate traces and vias → strip dry film → selectively remove exposed seed copper → perform optical and electrical inspection. mSAP follows a similar sequence but generally starts with carrier-supported ultrathin copper foil. Depending on the design, hole metallization, via filling, and surface pre-plating may also be included. “Additive” does not mean completely free of etching: final seed-layer removal remains critical to linewidth control. [1][2][7]

What has changed by 2026?

First, the objective has moved from making fine traces to producing them consistently across more layers and larger areas. SAP has long been used in IC package substrates; mSAP was not invented in 2026 either. Discussions once often reduced fine-line capability to minimum line/space (L/S). Advanced smartphone HDI, SLPs, and AI/high-performance-computing packages now simultaneously test multilayer registration, microvia reliability, copper-thickness uniformity, and defect rates. AT&S's 2026 discussion of mSAP places it in this context of miniaturization and high-speed data connectivity. [3][4]

Second, imaging, dry film, and inspection must improve together. As spacing shrinks, dry-film adhesion, opening sidewalls, compensation for dimensional changes, and defect detection all directly affect the finished copper traces. KLA introduced direct-imaging and inspection solutions for large, high-layer-count organic substrates in 2024. Qnity demonstrated dry film for direct imaging of fine substrate traces in 2025. In 2026, SCREEN introduced equipment that uses lasers to remove shorts and excess copper. These dates describe product announcements. Equipment resolution or demonstration-sample figures cannot be treated as customer-product volume-production yields. [5][6][8]

Third, thinner base copper makes the process window increasingly dependent on coordination across operations. A thin seed layer reduces erosion of plated traces during flash etching and helps preserve a more rectangular profile. Yet continuous conductivity and adhesion must still be maintained at microvia sidewalls and bottoms. A solution described by MKS/Atotech in 2025 integrates laser drilling, electroless copper, electroplating, and differentiated etching for advanced SAP and mSAP. Its public information refers to supporting advanced SAP development at ≤5/5 μm. This is a development direction, not evidence that ordinary PCB factories routinely mass-produce 5/5 μm circuitry. [7]

Fourth, new methods address the conflicting requirements of a thin surface layer and sufficient copper coverage inside the via. In June 2026, Elephantech announced DS-SAP: it first forms an ultrathin seed layer on the insulating surface, then uses copper nanoparticle ink to improve conductive coverage inside microvias. Published material shows cross-sections and subsequent plating results. It should currently be treated as a publicly demonstrated process direction, not a production standard that has comprehensively replaced established SAP. [9]

Five challenges for PCB, CCL, and substrate suppliers

1. Materials must combine low loss with adhesion. High-speed signals favor smooth copper surfaces and low-dielectric-loss materials, but reducing roughness too far can make copper-to-resin bonding more difficult. Ultrathin copper foil for mSAP and insulating build-up films for SAP must balance roughness, peel strength, heat resistance, and dimensional stability. CCL and materials suppliers must evaluate more than Dk and Df: they need joint validation with downstream laser drilling, desmear, seed-layer formation, and plating conditions. [10][11]

2. Flash-etch tolerance is shrinking. Residual seed copper between traces can cause shorts. Excessive etching narrows traces, damages sidewalls, and may open fine conductors. Base-copper thickness and uniformity, etchant condition, and line speed consequently become more important. This is why thin seed layers and highly selective etchants continue to receive attention. [1][7][9]

3. Microvias and surface traces cannot be optimized separately. Excess surface copper makes fine-line flash etching harder, while insufficient copper can leave discontinuities at via bottoms. Incomplete filling affects stacked-via and thermal-cycle reliability. Equipment suppliers, chemistry suppliers, and board manufacturers must jointly verify hole diameter, aspect ratio, desmear, electroless copper coverage, fill dimples, and reliability testing. An attractive circuit cross-section alone is insufficient for qualification. [7][9][12]

4. Larger boards and more layers amplify registration problems and yield losses. Every additional fine-line and microvia layer introduces opportunities for dimensional change, warpage, misregistration, and contamination to accumulate into scrap. Turning fine-line capability into reliable delivery requires process-capability statistics, linewidth and copper-thickness measurements, AOI defect classification, electrical testing, and traceability across operations. [5]

5. Investment and quotations must reflect a complete, production-capable specification. Ultrathin copper foil, low-loss build-up materials, high-resolution imaging, clean environments, precision plating, and inspection all require investment. Achieving a minimum L/S at one point does not establish a competitive whole board. Better questions when assessing a job include: Which layers use SAP/mSAP? What L/S can be produced at the specified copper thickness, hole diameter, board dimensions, and layer count? How are registration tolerance, reliability, and yield validated? These questions reveal more about cost and lead time than the smallest advertised number. [1][5][7]

What the transition means

The evolution from subtractive processing to mSAP and SAP does not mean every PCB should pursue the same minimum linewidth. It gives different products suitable ways to achieve the required density. By 2026, competition extends to coordinated control of material interfaces, microvias, imaging, plating, flash etching, and inspection. For manufacturers, the real barrier is delivering sufficient yield and reliability consistently under the customer's complete board specifications.