How CPO Is Changing Next-Generation PDs and TIAs: From Faster Optical Lanes to Optoelectronic Integration

As optical communications products move from 800G toward 1.6T and 3.2T, it is tempting to attribute every advance to CPO. Yet two optical engines labeled 3.2T may use very different architectures: one could have sixteen 200G optical lanes and another eight 400G lanes. Aggregate capacity is the same, but the receiver’s required per-lane speed differs by a factor of two.[1,2]

Two forces are driving next-generation receivers. AI infrastructure demands more transmission capacity, while CPO requires photonic and electronic components to operate together in a more confined space. The former raises per-lane performance requirements; the latter increases the importance of co-design, packaging, cooling, and testing. They reinforce each other but are not equivalent.

This article focuses on single-mode, intensity-modulation/direct-detection (IMDD) receivers for data centers. Long-reach coherent receivers and multimode VCSEL links are excluded from the same performance comparison.

1. PDs and TIAs Remain Essential in CPO

An optical receiver performs two tasks: it converts an optical signal into current, then converts that weak current into a voltage signal that downstream circuits can process.

The photodetector or photodiode (PD) handles the first task; the transimpedance amplifier (TIA) handles the second. Depending on the architecture, downstream circuitry then performs equalization, data decisions, and clock recovery.[3,4]

CPO changes where these functions are integrated and their distance from the main chip. Some designs remove the standalone DSP inside a pluggable module, but photodetection and current amplification still remain. The corresponding circuits also need not continue to be sold as separate chips. NVIDIA identifies shorter electrical paths and elimination of the standalone module DSP as sources of energy savings in its CPO explanation.[5]

It therefore does not follow that “CPO reduces component count” means PDs or TIAs are no longer needed. More useful questions are who designs these functions, which processes manufacture them, and who integrates them into optical engines.

2. Distinguish Aggregate Module Capacity From Optical Lane Rates

Equal Aggregate Capacity Does Not Mean the Same Receiver Generation

When rates are measured on the same basis:

Aggregate unidirectional rate = number of optical lanes × rate per optical lane.

For example, 1.6T can comprise eight 200G optical lanes or four 400G lanes. The latter demands more speed from each PD and each TIA channel; the former requires the package to accommodate more receive channels.

These examples cover pluggable modules and CPO optical engines; they do not imply the same form factor, standard, or production maturity. NVIDIA’s publicly described Spectrum-X Photonics optical engine uses sixteen transmit and sixteen receive lanes, providing 3.2T in each direction. MACOM’s 3.2T chipset targets the eight-lane, 400G/lane generation.[1,2]

A transceiver described as 1.6T usually provides 1.6T in each direction. Transmit and receive capacity should not be added together and relabeled 3.2T. Comparisons must also specify whether they refer to a switch chip, complete package, individual optical engine, or single pluggable module.

One Optical Lane Does Not Necessarily Mean One Fiber

Parallel optics can carry lanes on separate fibers, while wavelength-division multiplexing (WDM) allows several wavelengths to share one fiber. Optical lane counts, wavelength counts, and fiber counts are therefore not interchangeable.

Electrical lane counts can also differ from optical lane counts. Broadcom’s Taurus BCM83640 is a 1.6T DSP with an 8:4 architecture, pairing eight 200G-generation electrical lanes with four 400G-generation optical lanes. The PD receives the optical-side signal; the electrical side’s 200G cannot simply be taken as the PD requirement.[6]

Gb/s, GBd, and GHz Measure Different Things

MACOM specifies 224 GBd PAM4 for the MARP-BP224, equivalent to a raw bit rate of 448 Gb/s and positioned for the 400G/lane generation. Eight lanes at 448 Gb/s sum to 3.584 Tb/s raw, a different basis from the “3.2T chipset” nominal capacity. Actual net payload depends on the interface and coding definitions.[2,7]

This is why a “200G PD” or “1.6T TIA” calls for further questions: does the first refer to each lane, and does the second merely identify the intended module capacity? A larger number does not necessarily mean more advanced per-lane technology.

3. Which Changes Does CPO Accelerate?

If optical lane rate, modulation, wavelength, reach, and optical power budget remain the same, moving a receiver next to the main chip does not suddenly double its bandwidth requirement. Marvell explicitly says its 200G/lane TIA can be used in pluggable modules or integrated into CPO optical engines, demonstrating technical continuity.[3]

However, continuity of basic functions does not mean simply changing the enclosure. A new integration location requires performance and power budgets to be reallocated across circuits and packaging.

These directions are visible in Semtech’s hybrid PD–TIA assembly, ST’s PIC100 TSV roadmap, and NVIDIA’s optical/electrical stacking and shared thermal design. They also show that CPO’s central challenges span devices, circuits, and manufacturing flows.[1,8,9]

4. Next-Generation PDs Place More Emphasis on Performance With the TIA

High Bandwidth Must Be Considered Alongside Receiver Sensitivity

For a high-speed PD, shorter carrier travel distances, controlled junction capacitance, and reduced interconnect parasitics can improve speed. Device geometry also affects light absorption, coupling, and manufacturing tolerances. Practical designs must balance bandwidth, responsivity, dark current, and reliability.

Responsivity measures the photocurrent generated by a given optical power, commonly in A/W. Dark current is the current that remains without incident light. Receiver sensitivity is the minimum optical power the complete receive chain can detect at a specified error rate; it cannot be determined from a single PD parameter.

Albis’s PD50Y1 is an InGaAs/InP PD for 200G PAM4. Its public specifications include 50 GHz bandwidth per channel and 0.8 A/W responsivity at 1310 nm, with a backside integrated lens to improve coupling. MACOM’s MARP-BP224 targets 224 GBd PAM4 and lists carrier-transit-time-limited bandwidth above 100 GHz.[7,10]

The bandwidth definitions and measurement conditions may differ, so 50 GHz versus 100 GHz alone cannot rank the materials. The relevant comparison is power consumption and receive performance at the target rate after combining the PD with a TIA, packaging, and downstream equalization.

Ge and InGaAs Represent Different Integration Choices

InGaAs PDs are commonly fabricated in an InP material system and supplied as individual dies, arrays, or submount components before assembly with TIAs. Ge PDs are commonly integrated with silicon waveguides and other optical functions inside a photonic integrated circuit (PIC), using selective germanium growth in a silicon-photonics process.[4,10]

Ge’s appeal lies in manufacturing and integration within a silicon-photonics platform; it does not mean every performance measure must be superior to InGaAs. InGaAs can also enter optical engines through heterogeneous integration. CPO does not mandate a switch to Ge.

Similarly, silicon-photonics pluggable modules are already an important product direction. ST’s PIC100 targets 200G/lane, 800G, and 1.6T pluggable applications, and its white paper explicitly discloses integrated Ge PDs.[11]

Ge PDs and SiGe TIAs must also be distinguished. In the former, germanium is the light-absorbing material; in the latter, silicon-germanium is part of the electronic-circuit process. A SiGe TIA does not establish that the accompanying PD is also made from Ge.

5. TIA Competition Extends to the Packaging Interface

The Short Connection From PD to TIA Becomes a Design Priority

The signal leaving a PD is weak. Parasitic capacitance and inductance from contacts, bond wires, and traces affect frequency response. At higher per-lane speeds, the PD-to-TIA connection itself is part of the receiver design.

Marvell’s 200G/lane hybrid approach flip-chips the PD directly onto the TIA input while retaining wire bonds at the output. Semtech’s GN1834D similarly uses 2.5D assembly with flip-chip connections at the critical PD–TIA interface and wire bonding at the output.[3,8]

Such techniques also support the evolution of high-speed pluggable products; flip-chip technology should not all be treated as exclusive to CPO. CPO further increases the need for co-design across photonics, electronics, and packaging.

Linearity, Equalization, and Power Need to Be Reallocated

PAM4 represents data using four amplitude levels, so the receive chain must preserve the distinctions among them. TIA noise, linearity, gain, and frequency response all affect reliable downstream decisions.

In architectures without a standalone module DSP, interaction between the TIA and the main chip’s receive circuitry becomes more direct. This does not mean all CPO designs use the same circuit or that equalization disappears. Designers need to decide where each function belongs.[5,12]

MACOM’s next-generation quad-channel TIA, with digital controls for bandwidth, output amplitude, peaking, and gain, illustrates the move toward adjustable receiver platforms.[2]

Power figures also need matching measurement boundaries. If a receive block consumes 1 pJ per bit, it would use 1.6 W at 1.6 Tb/s—a simple arithmetic example. If one supplier reports only TIA power and another reports optical-engine power including lasers, drivers, and control circuits, the two pJ/bit figures cannot be directly ranked.

6. Which Products Are the Major Suppliers Advancing?

The following tables distinguish progress by specific products and platforms. Component availability, sampling, demonstrations, and platform volume production are different milestones and cannot substitute for one another.

PD and Receiver-Electronics Suppliers

The table shows component suppliers moving from individual parts toward more complete receive-chain combinations. However, availability of 400G/lane components does not mean every CPO or pluggable product using them is already shipping in volume.

Silicon-Photonics Platforms and Optical-Engine Suppliers

OpenLight’s original announcement targeted Q4 2026 for 3.2T beta samples. Merely entering that quarter does not establish delivery. Likewise, volume production of ST’s PIC100 platform does not mean its subsequent TSV platform and every customer product have entered production simultaneously.[9,17]

7. How Might the Upstream Supply Chain Change?

From the materials perspective, discrete InGaAs PDs typically involve compound-semiconductor substrates, epitaxy, device fabrication, and packaging. Integrated Ge PDs are part of a silicon-photonics PIC process. Both routes still require receiver electronics, optical coupling, assembly, and testing; they are not entirely isolated industries.[4,10,11]

Public company-level relationships already illustrate this division of labor:

GCS’s latest annual report still identifies major suppliers by codes. Although it links increased purchases from “Company N” to optical communications demand, it does not disclose the name. Supply-chain research can identify purchasing concentration and business relevance, but cannot fill in a company name from a code.[13]

For manufacturers, future competition may increasingly center on several capabilities: providing accurate PD models and package-design data, jointly optimizing interfaces with TIA suppliers, screening good parts before assembly, and consistently controlling multichannel optical-engine performance. This is an industry interpretation drawn from the integration examples above, not a checklist of capabilities that all suppliers have already achieved.