INDUSTRY ANALYSIS
Why M9/M10 and CPO Are Advancing Together: Material Demand in Next-Generation AI Servers
CPO shortens high-speed electrical connections between switch ASICs and optical engines, but that does not mean AI servers can dispense with low-loss PCBs. NVIDIA's disclosed architectures and materials suppliers' information suggest that next-generation systems are more likely to divide the work among M9/M10 laminates, copper cables, and optical links. Advanced laminates still have room to grow, but each board and channel must be assessed separately. CPO adoption does not automatically mean declining materials demand, and M10 development targets should not be treated as confirmed orders.
Information compiled through September 29, 2026. This article focuses on NVIDIA AI servers and their associated switches. Future impacts are engineering and demand inferences based on publicly disclosed architectures. M9/M10 follow the industry's material-grade terminology; actual selection still requires comparison of specific products, test conditions, and PCB stackups.
Data rates in AI servers continue to rise, making signal loss on circuit boards increasingly difficult to manage. Materials suppliers are pursuing lower-loss copper-clad laminates, while system designers develop CPO, near-chip cabling, and other interconnect approaches. As both paths advance, a question arises: if high-speed signals can bypass more of the PCB, why is M9 still needed, and why continue developing M10?
The answer lies in the different signal paths within a system. CPO can remove particular channels' dependence on long PCB traces. High-speed electrical connections that remain on the board may continue to drive material upgrades. Assessing next-generation demand therefore starts with where signals convert from electrical to optical, and how many critical paths must still run through the board.
CPO changes the location of optical/electrical conversion
In a conventional pluggable-optics architecture, a signal travels from the switch ASIC across the PCB to the chassis panel, then enters an optical module for conversion to light. CPO moves the optical engine next to the switch ASIC, bringing data into fiber earlier. This shortens the lossy electrical path and can reduce the burden on some signal-compensation circuits. [1]
This change has reached the product stage. In June 2026, NVIDIA announced that Spectrum-X Ethernet Photonics had entered volume production. A commercial alternative therefore exists for some traditional high-speed electrical channels and pluggable optical modules on the switch side. [2]
However, this establishes a change in those connections, not that the entire switch PCB has been downgraded to a lower material grade. It certainly does not establish that every board inside the server no longer needs M9/M10. The remaining critical channels, power delivery, and manufacturing reliability still need separate validation.
The same AI server can increase both PCB and optical connections
NVIDIA's disclosed Vera Rubin NVL72 design illustrates this division of roles. Inside the tray, a PCB midplane connects compute modules, ConnectX-9 network adapters, and BlueField DPUs. At the rear of the rack, the NVLink spine still uses pre-integrated copper cable cartridges containing approximately 5,000 copper cables. [3]
“Cable-free inside the tray” and “copper cables in the rack” can therefore both be true. Replacing a connection with a PCB at one location may increase board demand, while adopting CPO elsewhere may reduce long, high-speed electrical traces. A change in one component cannot determine the materials demand of all PCBs in the system.
Public roadmaps also support the coexistence of several approaches. When discussing Feynman at GTC 2026, NVIDIA referred to both copper connections and a CPO-based scale-up architecture. [4] On that evidence, the more reasonable next-generation baseline is a division of work among advanced laminates, more mature laminates, copper cables, and optical links according to the signal path, rather than a single material or interconnect technology across the whole system.
Which boards actually need M9/M10? Research estimates and final production decisions must be distinguished
NVIDIA has not publicly disclosed a complete board-level materials list. A more specific public comparison comes from TrendForce research in November 2025, which identified some midplanes and CX9/CPX boards as M9 applications, while listing M8U for the switch tray. [5] This helps identify the direction of material upgrades, but it reflects research at that time and cannot be applied directly to every later product revision.
Materials suppliers' disclosures address a different level of evidence. In its 2026 interim report, Nanya New Material Technology described its M9 materials as entering qualification and new-product introduction with several customers, and positioned M10 as a material solution for next-generation high-speed backplanes. [6] This demonstrates continued development and introduction of advanced materials, but does not establish qualification on specific NVIDIA boards or show that other suppliers have reached the same stage.
The possible effects can be organized as follows. Future impacts in the table are engineering inferences, not announced plans by manufacturers to downgrade materials.
| Board or critical path | Publicly available materials information | Replacement status and possible impact |
|---|---|---|
| Long traces from a network switch ASIC to front-panel optical modules | Material grades have not been fully disclosed across models | Commercial alternatives exist. CPO bypasses these long electrical channels, but the main board remains. Any material downgrade requires separate validation. |
| PCBs in switch-side pluggable optical modules | Optical modules cannot all be assumed to use the same material grade | Partial replacement exists. Corresponding CPO ports no longer require the original complete pluggable transceiver; optical engines still need packaging and substrates. |
| Long, high-speed traces on NVLink switch boards | Early research listed M8U; use of M9/M10 across all revisions has not been confirmed | Partial replacement is possible. Flyover, CPC, or CPO may reduce the number of advanced-material layers or defer upgrades on some channels. |
| Large high-speed electrical or orthogonal backplanes | Suppliers position M10 for next-generation high-speed backplanes; adoption in specific models remains unconfirmed | Most dependent on architectural choices. Retaining long electrical traces strengthens the case for material upgrades; extensive use of cables or optical links could reduce demand. |
| PCIe midplane inside a Rubin tray | Early research identified some midplanes as M9 applications; official disclosures confirm the midplane's connectivity role | More likely to remain. Switch-side CPO does not directly remove host-to-NIC/DPU electrical connections. |
| CX9 and later network-adapter boards | Early research identified CX9 as an M9 application; not all revisions' stackups are public | Localized replacement is possible. Network-side traces may shorten, while host-side PCIe still needs to be addressed separately. |
| GPU/CPU compute boards and particular accelerator boards | Early M9 information for CPX cannot be extended to all compute boards | The overall board is more likely to remain. Some high-speed I/O can move off the PCB, but whether the remaining channels require M9/M10 still needs validation. |
The architecture and materials information above comes from NVIDIA, TrendForce, and materials suppliers, respectively. Their disclosures support different conclusions. “Suitable for an application,” “under development,” “in customer qualification,” and “adopted in a system in volume production” must not be treated as equivalent. [1][2][3][5][6]
Cables are another alternative that advanced CCL suppliers must track
Reducing PCB loss does not have to wait for CPO. Flyover uses low-loss copper cables to bypass longer board-level traces, while co-packaged copper (CPC) can move the connection point closer to the chip package. At DesignCon 2026, Samtec demonstrated a CPC prototype and loss measurements for a 448 Gbps channel, providing a concrete development example of changing the transmission path. [7]
The critical issue is the channel that determines material selection. If only a few long, high-speed channels require a lower-loss laminate, removing those channels may allow the remaining design to qualify with the existing material. Conversely, if a critical channel remains on the PCB and the existing material cannot meet its loss budget, the need to upgrade may persist.
The proportion of traces moved off the board therefore cannot directly predict the extent of a material downgrade. What matters is whether the channels constraining material selection have been addressed.
Advanced laminates still have growth potential, but the demand evidence for M9 and M10 differs
As long as some high-speed backplanes, switch boards, and midplanes continue carrying electrical signals at higher rates, low-loss materials retain opportunities for upgrades. If AI system shipments, PCB area, or the number of advanced-material layers also increase, those gains may outweigh reductions caused by moving some channels to fiber or cables.
Supplier investment reflects continued expectations for growth in high-speed board materials. In March 2026, Panasonic announced an investment of approximately ¥7.5 billion in additional MEGTRON production lines in Guangzhou and reiterated plans to expand global capacity. The announcement covers several material generations, however, and cannot by itself establish shipment growth for M9 or M10. [8]
A conclusion more consistent with the public evidence is that M9 has opportunities to grow as qualification and introduction broaden. M10 addresses future requirements such as faster electrical backplanes, but its production timing and scale of use still depend on material qualification and final architectural choices. [6]
CPO's substitution for specific applications is compatible with growth in the overall advanced CCL market. Estimates of materials demand should at least consider system shipments, PCB area per system, the number of advanced-material layers, and the actual share using M9/M10.
Publicly disclosed architectures support the parallel development of M9/M10 and CPO. For materials demand, the key distinction is which high-speed signals must still travel through PCBs and which have moved to cables, fiber, or in-package connections. Designs that retain high-speed electrical channels may continue to drive material upgrades. Designs that substantially change the interconnect path may reduce advanced-laminate consumption or defer upgrades. Both directions will shape materials demand in next-generation AI servers.
Sources & notes
- Information compiled through September 29, 2026. Source descriptions are retained from the Chinese article. Where it did not supply a URL, no link has been inferred.
- [1] NVIDIA, A New Era in Data Center Networking with NVIDIA Silicon Photonics-based Network Switching, March 27, 2025. Explains CPO integration location, shorter electrical connections, and differences from conventional pluggable modules.
- [2] NVIDIA, NVIDIA GTC Taipei at COMPUTEX: Live Updates on What's Next in AI, June 1, 2026; section “NVIDIA Spectrum-X Ethernet Photonics Ramps to Production.”
- [3] NVIDIA, NVIDIA Vera Rubin POD: Seven Chips, Five Rack-Scale Systems, One AI Supercomputer. Page publication date: March 16, 2026; content as accessed for the original article. Describes the tray PCB midplane, NIC/DPU connections, and NVLink copper-cable spine.
- [4] NVIDIA, NVIDIA GTC 2026: Live Updates on What's Next in AI, March 2026; section “Vera Rubin and Beyond.” Describes copper connections and the CPO scale-up direction for Feynman.
- [5] TrendForce / Topology Research Institute, research on Rubin's cable-free architecture and high-layer-count HDI architectures for ASICs driving the PCB industry's role in computing, November 20, 2025. The board/material mapping reflects research at that time, not a final production bill of materials for every later model.
- [6] Nanya New Material Technology Co., Ltd., 2026 Interim Report, announced August 29, 2026; management discussion and analysis and core-technology sections. One company's qualification progress does not establish the progress of the entire industry or all suppliers. Full company disclosure republished by Sina Finance.
- [7] Samtec, 448 Gbps Co-Packaged Copper Channel, March 11, 2026. CPC prototype and channel-loss measurements at DesignCon 2026, not an announcement of NVIDIA volume-production adoption.
- [8] Panasonic Industry, Panasonic Industry Announces an Investment of 7.5 Billion yen for a New MEGTRON Circuit Board Materials Production Line to Address Growing AI Server Demand, March 4, 2026. The expansion covers multiple material generations and is not a demand breakdown for M9/M10.