HBM4 and HBM4E Technology and Supply Chains: How the Three Major Suppliers Combine Memory Processes and Advanced Packaging

What is HBM4E? Product generations and process generations are different

As AI accelerators become faster, memory must deliver data quickly enough to keep them supplied. High-bandwidth memory (HBM) vertically stacks DRAM dies, transfers signals through through-silicon vias (TSVs) and inter-die contacts, and connects to GPUs or other accelerators through high-density packaging. [1][16]

HBM4E is the enhanced generation following HBM4. Micron's HBM4E and SK hynix's or Samsung's HBM4 are not different names for products of the same generation. All three suppliers have their own HBM4 and subsequent HBM4E roadmaps. [3][4][6][9]

A product upgrade does not require every manufacturing stage to change technology simultaneously. HBM process analysis should distinguish at least three parts:

1. DRAM dies: store data. Their process and design affect capacity density, power consumption, and yield.

2. Logic base die: sits beneath the stack and handles interface and control functions. It is also becoming an important location for customization.

3. Stacking and packaging: bonds the dies and addresses electrical connections, thickness, cooling, and structural reliability.

“1c DRAM,” “4 nm base die,” and “MR-MUF” therefore describe three different dimensions. They cannot be compared along one process-node scale.

Principal differences between HBM4 and HBM4E

An important change from HBM3E to HBM4 is the expansion of the external data interface from 1,024 bits to 2,048 bits. HBM4E builds on that architecture with higher transfer rates, capacity, and energy efficiency, while expanding customization options. [1][13]

Sources: [1][4][5][6][7][8][13][25]. Speeds and capacities are supplier examples, not guaranteed specifications shared by every product. A sample's maximum speed is not necessarily its operating speed in a customer's system.

For a 2,048-bit interface operating at 12 Gbps per data pin, theoretical bandwidth is 2,048 × 12 ÷ 8 = 3,072 GB/s, or approximately 3.07 TB/s. This is an interface calculation; real applications also depend on the controller, access patterns, and system design.

Comparing the three suppliers' HBM4 and HBM4E processes

The differences center on when DRAM processes advance, who manufactures the base die, and how established packaging capabilities are extended.

Process names need separate interpretation. 1b, 1c, 1β, and 1γ are suppliers' DRAM technology-generation names, not “1 nanometer.” Names from different companies cannot be directly converted into identical physical dimensions. The base die's 4 nm label is a logic-process designation, a different basis of comparison from a DRAM node.

SK hynix: DRAM, logic foundry, and MR-MUF advance together

SK hynix's HBM4 uses 1b DRAM and a logic base die developed with TSMC. HBM manufacturing therefore involves both memory processing and logic foundry work. The partners also cooperate on HBM integration with CoWoS. [1][2]

SK hynix's announced 12-high 48GB HBM4E samples continue to use Advanced MR-MUF. This demonstrates that higher capacity and speed can accompany continued improvement of an established stacking technology. [4]

Samsung: upgrading through design optimization while retaining 1c and 4 nm

Samsung combines DRAM, logic foundry, and packaging capabilities. Both its HBM4 and announced HBM4E samples use 1c DRAM and 4 nm base dies. [5][6]

Samsung HBM4E therefore cannot be summarized as “requiring 1d DRAM or a 2 nm base die.” Upgrades in the public samples include memory and logic architecture optimization, higher capacity, and improvements in low-power and packaging design. Later customized versions should be assessed through their individual announcements. [6]

Micron: from internal base-die manufacturing to cooperation with TSMC

Micron's HBM4 uses 1β DRAM and internally designed and manufactured base dies. HBM4E moves to 1γ DRAM and cooperation with TSMC on standard and customized base dies. Among the three suppliers, this represents a particularly clear change in manufacturing responsibilities. [8][9]

Changes in 1γ include EUV lithography and a new generation of high-k metal-gate technology. Process evolution therefore includes both patterning and transistor technology. Improvements reported for general DRAM cannot, however, be directly treated as HBM4E finished-product performance or yield gains. [11]

In its September 2026 earnings materials, Micron disclosed work with NVIDIA on NVHBM, a customized HBM4E implementation intended for later GPU and NVLink Fusion platforms. This is public progress in customization, not evidence that all HBM4E uses the same design. [10]

How stacking works: MR-MUF, TC-NCF, and hybrid bonding

“12-high” or “16-high” usually counts the DRAM dies; a base die sits underneath. Thinner dies and taller stacks increase the importance of bonding precision, warpage control, thermal management, and yield.

HBM4E does not require every supplier to adopt hybrid bonding throughout. SK hynix's HBM4E samples retain MR-MUF. Samsung's hybrid copper bonding must be distinguished between sampling and commercialization plans. Micron's detailed HBM4/HBM4E bonding flows are not fully disclosed in the primary sources used here; a definitive equipment and materials list should not be filled in by assumption.

The comparison also should not be reduced to whether a process “uses adhesive.” MR-MUF and TC-NCF materials primarily provide protection, insulation, and mechanical support. Hybrid bonding changes the die-bonding interface; it does not imply that the entire package no longer needs polymers.

Process supply chain: who does what?

The HBM supply chain spans product design and wafer fabrication, TSV processing and stacking, and testing and system packaging. The following distinguishes confirmed products or partnerships, confirmed HBM-related business, and technical capability alone. Relevant capability does not establish an HBM4 or HBM4E order from a particular memory supplier.

Design, DRAM, and logic base dies

GUC's 3 nm HBM4 IP demonstration does not establish that a memory supplier's base die uses 3 nm. The HBM controller/PHY on the accelerator side and the base die underneath the memory stack are different design locations. GUC's announcement confirms an IP platform and packaging demonstration, not that it designed a base die for a named HBM manufacturer. [15]

Lithography, TSVs, thinning, bonding equipment, and materials

Bonding equipment and packaging materials need joint process tuning. The name “TC Bonder” alone does not establish that an entire line uses TC-NCF. Its actual role—placement, pre-bonding, or final bonding—must be identified.

Testing, system packaging, and substrates

HBM stacking and CoWoS: two packaging stages with different responsibilities

A common source of confusion is the distinction between making an HBM product and integrating HBM into an AI accelerator package.

The first stage combines DRAM dies, TSVs, and a base die into an HBM stack. It involves die thinning, bonding, underfill, and memory testing.

The second integrates finished HBM with a GPU/ASIC through an interposer or other high-density interconnect structure and connects that assembly to a package substrate. CoWoS belongs to this level of integration. ABF substrates also serve this larger package structure. [2][16][23]

TSMC can consequently have two roles in the same supply chain: base-die foundry manufacturing and advanced accelerator packaging. These are different jobs. Substrate suppliers, assembly/test providers, and HBM manufacturers must likewise be identified by their separate business positions.

How do downstream customers influence HBM technology choices?

HBM specifications and production schedules generally require joint development and qualification with accelerator platforms. Customers consider power, cooling, usable capacity, package space, and stable supply alongside maximum bandwidth.

Specific public examples exist: Micron announced HBM4 for NVIDIA Vera Rubin; SK hynix displayed Rubin-related products with its HBM4; and Samsung's memorandum of understanding with AMD covers cooperation toward a primary HBM4 supply role for AMD Instinct MI455X. [7][24][25]

These link products to platforms, but demonstrations, memoranda of understanding, completed qualification, and high-volume shipments represent different stages. They cannot be used interchangeably. Micron's NVHBM disclosure also shows customized HBM4E deepening cooperation between memory suppliers and accelerator designers. [10]