SUPPLY CHAIN HANDBOOK

Semiconductors: design, fabrication and packaging

Prepared by IndustryAtlas Editorial principles & corrections

Read design, wafer fabrication, packaging and testing together with their materials and equipment. Process order and company business models are different views; one company can participate in several stages.

Most recent source review: 2026-10-30

Reading guide revised: 2026-10-30

Why does a fabricated chip still need a separate packaging supply chain?

Wafer fabrication creates devices and wiring within a chip. Packaging connects its tiny contacts to other dies or a system board, while addressing power, protection and heat. Dense exchanges between logic and memory make packaging part of system architecture. Design data, processed wafers, usable dies and packaged components are distinct deliverables. Inspection and electrical testing occur throughout this journey to help prevent defects from entering more costly integration steps.

IC design, EDA and IP → Wafer fabrication
Design teams translate functions into verified circuits and layouts compatible with a process. Fabrication turns the design into physical structures through repeated deposition, lithography, etching and measurement.
Processed wafers and test data → Die selection and packaging
Wafer testing supplies electrical information about individual dies. Downstream operations select and assemble them; substrates, interposers or redistribution layers bridge their fine contacts to the next integration level.
Packaged components → Board-level systems
Packaging provides assembly interfaces and interconnects. Final component testing checks packaged functionality, while board-level integration validates the combined signal, power and thermal behavior.

What changes the choice?

Compare packaging routes by contact density, die combinations and heat removal before size and cost. CoWoS illustrates dense logic–HBM integration, but is not a universal requirement for chips.

Sources for this overview

Semiconductor supply chain

IC Design

Turning functional needs into circuits and physical layouts

IC design translates computing, communication or control requirements into circuits and layouts. Fabless companies can outsource wafer fabrication; other businesses combine design and manufacturing. Chip design, wafer fabrication and end-product assembly are distinct roles.

Entry sources reviewed: 2026-10-30

EDA and IP support different parts of design

EDA supplies design and verification tools; reusable IP supplies functions that teams integrate into a chip. Both must fit the chosen process and implementation.

SoCs and GPUs describe chip functions, while IC design describes the work that produces them.

Distinction: Fabless does not mean a company lacks hardware expertise. Designers and fabs specialize in different stages.

Company roles

MediaTek · Taiwan · Example role · IC design and mobile computing platforms
Designs processors and integrated platforms for phones and other devices; listed here for design.
Product / role source
Realtek · Taiwan · Example role · Communications and multimedia IC design
Ethernet and other communications and multimedia chips.
Product / role source
Sources reviewed: 2026-09-27
Novatek · Taiwan · Example role · Display and imaging IC design
Display-driver ICs and imaging-related chips.
Product / role source
Sources reviewed: 2026-09-27
Qualcomm · United States · Example role · IC design, computing and communications platforms
Snapdragon and other platforms integrate computing, imaging and communications.
Product / role source

Sources

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EDA and Semiconductor IP

Design tools and reusable functions before chip manufacturing

EDA software supports circuit design, simulation, verification and implementation. Semiconductor IP supplies reusable functions such as processor cores and interfaces. They work together but are different products, and neither is a finished manufactured chip.

Entry sources reviewed: 2026-09-26

Design must fit the manufacturing process

Design data must obey the selected fabrication rules. Tools help implement and verify a design but do not replace process integration.

Distinguish licensed design functions from software used to create and validate the overall circuit.

Distinction: An IP supplier need not fabricate chips, and an EDA company is not the same role as a foundry.

Company roles

This stage includes EDA tools and IP licensing, which are different roles; not every company offers all products.

Andes · Taiwan · Example role · Processor IP
AndesCore processor and SoC platform IP for chip-design integration.
Product / role source
Synopsys · United States · Example role · EDA software and semiconductor IP
Chip-design and verification tools and semiconductor IP products.
Product / role source

Sources

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Semiconductor Packaging

Connecting and protecting dies within a usable component

Packaging connects dies to external systems while addressing protection, power, signals and heat. Wire bonding, flip-chip, fan-out and 2.5D or 3D integration are different approaches. CoWoS is one technology family, not the name for all packaging.

Entry sources reviewed: 2026-10-30

The connection back to boards

Some packages use IC substrates and connect to PCBs through solder balls or other structures. Substrate material and package integration have different roles.

Package architecture determines which materials and interconnects are required.

Capabilities can cross business categories

Outsourced assembly and test providers, foundries and integrated device manufacturers may each provide selected packaging capabilities.

A broad company category does not establish support for every package technology.

External assembly and wafer handoffs

Outsourced assembly can receive whole wafers for the contracted processing steps. Transport carriers and packing must match wafer or die condition.

The semiconductor logistics view connects wafer shippers, die carriers and inter-fab transport.

IC and packaging scrap recovery Silicon slurry recovery

Distinction: General packaging, package substrates and CoWoS must remain distinct to avoid implying every chip uses the same advanced package.

Company roles

ASE · Taiwan · Example role · Outsourced packaging services
IC packaging and integration services selected for product requirements.
Product / role source
Amkor · United States · Example role · Outsourced packaging services
Wire-bond, flip-chip, wafer-level and other packaging products and services.
Product / role source
TSMC · Taiwan · Example role · Advanced packaging
CoWoS and other advanced packaging capabilities, listed separately as manufacturing and integration roles.
Product / role source

Sources

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Wafer and Packaged-Device Testing

Electrical verification at several manufacturing stages

Wafer probing tests dies before they leave the wafer; final test checks packaged devices, and some products also undergo system-level testing. Testing is not a single step that begins only after packaging.

Entry sources reviewed: 2026-10-04

Electrical test and inspection answer different questions

Inspection finds manufacturing anomalies; electrical test verifies device operation against specifications. Test stages must suit the actual product.

Wafer, package and system-level checks can address different risks rather than duplicate one identical measurement.

Distinction: A company listed for testing does not necessarily handle every chip type or every customer.

Company roles

KYEC · Taiwan · Example role · Specialist chip testing
Wafer probing, final IC testing and burn-in services.
Product / role source
Sources reviewed: 2026-09-27
PTI · Taiwan · Example role · Semiconductor packaging and testing
Integrated wafer testing, packaging and final-test services.
Product / role source
Sources reviewed: 2026-09-27
ASE · Taiwan · Example role · Wafer and final testing
Wafer probing, final testing and system-level testing.
Product / role source
Amkor · United States · Example role · Wafer and package testing
Wafer-stage and post-packaging test services.
Product / role source

Sources

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Wafer processes & materials

Semiconductor Silicon Wafers

The processed substrate before transistors and circuits

Wafer-material suppliers grow high-purity single-crystal silicon, slice it and finish the surfaces for chip fabrication. The delivered wafer is not yet a completed chip and is unrelated to the CCL used in circuit boards.

Entry sources reviewed: 2026-10-30

Material production precedes device fabrication

The material supplier delivers a substrate; the chip fab creates devices and interconnects on it. Surface condition and wafer specifications must fit the downstream process.

This node focuses on silicon. SiC, GaN and other semiconductor platforms require their own substrate and process assessment.

A material input to power semiconductors

Silicon wafers can serve silicon power devices or GaN-on-Si epitaxy. Substrate specifications and epitaxy are process-specific; existing wafer examples do not establish every GaN supply contract.

Distinction: GlobalWafers and SUMCO supply wafer materials; TSMC and UMC perform a different role by fabricating devices on wafers.

Company roles

GlobalWafers · Taiwan · Example role · Semiconductor silicon wafers
Polished, epitaxial and other silicon wafers used as chip-manufacturing substrates.
Product / role source
FST · Taiwan · Example role · Silicon wafer manufacturing
Silicon wafer materials for semiconductors.
Product / role source
Sources reviewed: 2026-09-27
SUMCO · Japan · Example role · Semiconductor silicon wafers
Polished, epitaxial, SOI and other silicon wafer specifications.
Product / role source

Sources

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Wafer Fabrication

Repeated processing builds devices and interconnects

Wafer fabrication repeatedly deposits films, forms patterns, removes material, changes electrical properties and inspects results. Foundries manufacture for customers, while integrated device manufacturers combine their own product design and manufacturing.

Entry sources reviewed: 2026-10-30

Fabrication is a repeated sequence

Lithography, etching, deposition and metrology recur across layers alongside implantation, heat treatment, cleaning and planarization.

The map groups functions; it does not describe one pass through a simple assembly line.

A fabricated wafer is not the final product

Dies need electrical testing and, according to the product, singulation, packaging and further tests before use.

Manufacturing capability and business role must both be considered when reading company lists.

Wafer reclaim Organic solvent recovery TMAH developer recovery Waste acid regeneration Metal-bearing wastewater recovery

Distinction: TSMC, UMC and Micron can share a manufacturing node without sharing one business model or producing identical products.

Company roles

Foundries and IDMs both manufacture chips but differ in business models and product scope; no vendor is assumed capable of making every chip on the map.

TSMC · Taiwan · Example role · Pure-play wafer foundry
Manufactures wafers to customer chip designs, with additional capabilities including advanced packaging.
Product / role source
UMC · Taiwan · Example role · Pure-play wafer foundry
IC manufacturing for logic and specialty processes.
Product / role source
Micron · United States · Example role · Memory design and manufacturing (IDM)
Designs and manufactures memory and storage products; listed here for manufacturing its own products.
Product / role source

Sources

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Photomasks

Carrying the pattern used in lithography

A photomask carries the design pattern that an exposure system transfers to photosensitive material on a wafer. Mask design, fabrication and defect control influence the transferred result. A mask is not the photoresist itself.

Entry sources reviewed: 2026-09-26

Qualify capability for the platform

Photomask capability depends on the process platform, specifications and qualification. A general supplier label cannot establish suitability for every advanced technology.

Mask-making and photoresist supply remain separate steps in pattern transfer.

Distinction: Appearing in a photomask directory does not establish that a company supplies every EUV or advanced-node mask.

Company roles

Lists photomask roles without assuming that every company supports EUV or all advanced processes.

TMC · Taiwan · Example role · IC and microstructure photomasks
Photomask manufacturing and design-data processing services.
Product / role source
Photronics · United States · Example role · IC photomasks
Integrated-circuit photomasks for different lithography requirements.
Product / role source

Sources

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Process Chemicals and Gases

Specialized inputs throughout wafer fabrication

Fabs need photoresists, developers, cleaning chemicals, process gases and deposition precursors as well as wafers. Each step has its own purity, particle, metal-contamination and batch-stability requirements.

Entry sources reviewed: 2026-10-30

Qualification follows the intended use

A high-purity label does not make a chemical interchangeable across process steps. The chemistry and contamination requirements must fit the material and device being processed.

Separate chemical supply from the equipment and process integration that use it.

Organic solvent recovery TMAH developer recovery Chemical recovery systems Etch gases and chemical materials

Distinction: Photoresist, CCL resin and packaging compounds can all involve polymers, but their functions, locations and qualification conditions differ.

Company roles

Materials vary widely; vendors represent only their stated product roles, not supply of every process gas and chemical.

San Fu Chemical · Taiwan · Example role · Electronic-grade wet chemicals
Developing, etching, stripping and cleaning chemicals for ICs and other electronics; operates separately from San Fu Gas.
Product / role source
Tokyo Ohka Kogyo (TOK) · Japan · Example role · Photoresists and supporting chemicals
Photoresists and related high-purity chemicals for semiconductor lithography.
Product / role source

Sources

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Lithography

Pattern formation using masks, resist and exposure

Lithography combines a mask, photoresist and exposure system to form patterns for later processing. Coating, baking and development accompany exposure; other processes generally transfer the resulting pattern into the target material.

Entry sources reviewed: 2026-09-26

Exposure works within a process sequence

An exposure machine provides imaging capability but cannot make a chip by itself. Etching, deposition, cleaning and related steps complete the structures.

Read the selected exposure approach together with its mask, resist and process requirements.

Distinction: Not every chip or layer uses EUV, and lithography is not another name for all wafer fabrication.

Company roles

Verified exposure-system roles are listed first. Coating/developing, photomasks and photoresists have different equipment and material suppliers; the directory will continue to expand.

ASML · Netherlands · Example role · Lithography exposure systems
DUV, EUV and other lithography systems for wafer pattern transfer.
Product / role source

Sources

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Etching and Cleaning

Removing selected material or unwanted residues

Etching selectively removes material to form structures; cleaning removes contamination or process residues. Some chemical techniques overlap, but the purposes, equipment and acceptance criteria differ.

Entry sources reviewed: 2026-10-30

Identify the process location

Wet equipment can serve packaging and other wafer-level operations as well as front-end fabrication. Its role must be checked for the intended product.

Distinguish intentional pattern formation from surface preparation and residue removal.

Semiconductor etch equipment Conductor and transistor etch Dielectric and deep-hole etch Selective and atomic layer etch

Distinction: Wafer etching and PCB copper etching both remove material, but their scales, materials and equipment are not directly interchangeable.

Company roles

Wet-cleaning equipment and dry-etching systems are different products; one application does not establish every process capability.

GPTC · Taiwan · Example role · Wet etching and cleaning equipment
Single-wafer, batch and other wet-process equipment; suitability depends on the model and process.
Product / role source
Lam Research · United States · Example role · Dry etching equipment
Etch systems for selective material removal and fine-feature formation.
Product / role source

Sources

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Thin-Film Deposition

Adding controlled material layers to wafer structures

Deposition forms required materials on wafer surfaces or three-dimensional structures. Chip fabrication uses several film materials and methods; thickness, uniformity, coverage and impurity control affect the devices.

Entry sources reviewed: 2026-09-26

The structure determines the method

Material requirements, geometry and thermal budget call for different deposition approaches. A process name alone does not establish which is best.

Evaluate how the deposited layer covers the intended structure and fits the earlier and later process steps.

Distinction: Thin-film deposition is not PCB lamination. The scale and way layers are formed are different.

Company roles

Lam Research · United States · Example role · Thin-film deposition equipment
CVD, ALD and other systems forming conductive and dielectric films.
Product / role source
Applied Materials · United States · Example role · Thin-film and materials-engineering equipment
Deposition and other material-processing systems selected for the film and structure.
Product / role source

Sources

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Ion Implantation and Thermal Processing

Adjusting material properties within a controlled thermal budget

Ion implantation introduces selected ions into a material to control properties such as doping. Thermal processes can activate dopants, repair damage or change material behavior, within the constraints of the device and existing layers.

Entry sources reviewed: 2026-09-26

Higher temperature is not inherently better

Each thermal step affects structures already formed. Processing conditions must fit the device architecture and accumulated thermal history.

Implantation and later heat treatment perform related but distinct functions.

Distinction: Implantation modifies an existing material rather than simply depositing a new film on top.

Company roles

Applied Materials · United States · Example role · Ion implantation and thermal processing
Equipment for implantation, annealing and related material-modification processes.
Product / role source
Axcelis · United States · Example role · Ion implantation equipment
Purion implantation systems for different energies and applications.
Product / role source

Sources

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CMP Planarization

Chemical and mechanical control of surface topography

Chemical mechanical planarization removes excess material and controls surface height differences. Equipment, polishing pads, slurry and conditioning consumables must work together; the goal is more than a shiny surface.

Entry sources reviewed: 2026-09-27

Consumables and equipment have separate roles

KINIK diamond discs condition the polishing pad; they are not complete CMP machines. Slurry, pads, conditioners and equipment form a coordinated process.

Evaluate material removal and topography against the device process rather than surface appearance alone.

Distinction: Process CMP and the surface polishing of incoming silicon wafers are related concepts, but they do not use identical process conditions.

Company roles

KINIK · Taiwan · Example role · CMP diamond discs and pad-conditioning consumables
Diamond discs condition polishing pads to maintain removal rates and uniformity; not complete CMP machines.
Product / role source
PVI · Taiwan · Example role · CMP polishing pads
Semiconductor CMP pads and related consumables.
Product / role source
Sources reviewed: 2026-09-27
Applied Materials · United States · Example role · CMP planarization equipment
Chemical mechanical planarization systems for wafer-surface material removal and flattening.
Product / role source

Sources

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Metrology and Defect Inspection

Process feedback throughout chip manufacturing

Metrology measures dimensions, film thickness, alignment and other parameters; inspection locates anomalies that may reduce yield. Both occur throughout fabrication and feed results back into process control.

Entry sources reviewed: 2026-09-26

Process control differs from electrical testing

Metrology and inspection describe the manufacturing state. Electrical testing checks whether a device functions and meets specifications.

These methods complement one another; one cannot replace all the others.

Distinction: Measuring very small dimensions does not prove that every chip meets its functional or reliability requirements.

Company roles

KLA · United States · Example role · Process inspection, metrology and control
Defect inspection and metrology for wafers, masks and related processes.
Product / role source
Hitachi High-Tech · Japan · Example role · CD-SEM and defect inspection
Critical-dimension measurement, defect inspection and related data solutions.
Product / role source

Sources

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Packaging & substrates

IC Package Substrates

Bridging fine chip connections to the system board

An IC package substrate carries fine-pitch chip or interposer connections to a scale the motherboard can accept. It belongs to the package, not the server motherboard. Fine traces, microvias, flatness and dimensional control are central challenges.

Entry sources reviewed: 2026-10-04

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ABF Build-up Film

An insulating material used to build package substrates

Ajinomoto Build-up Film is an insulating film developed by Ajinomoto for package substrates. Substrate makers laminate and cure the film, create microvias and copper circuits, and repeat the build-up where needed. The film is neither a finished substrate nor a chip.

Entry sources reviewed: 2026-09-30

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CoWoS Advanced Packaging

Dense integration of logic, HBM and package substrates

CoWoS is a TSMC advanced-packaging technology family. It connects logic chips and components such as HBM through an interposer and then to a package substrate, concentrating many connections over short distances.

Entry sources reviewed: 2026-09-26

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High-Bandwidth Memory

Stacked DRAM with a wide data interface

HBM stacks multiple DRAM dies with vertical connections such as through-silicon vias. It is often placed beside high-performance processors on a shared package platform. Capacity measures stored data; bandwidth measures data moved per second.

Entry sources reviewed: 2026-10-03

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GPUs and AI Accelerators

Compute performance depends on more than the processor

GPUs process many operations in parallel. AI accelerator is a broader category that also includes purpose-built chips. Useful performance depends on memory capacity and bandwidth, communication, software and cooling as well as compute units.

Entry sources reviewed: 2026-10-30

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ABF Package Substrates

Build-up film processed into fine package interconnects

ABF substrates use ABF film as build-up insulation, with copper traces and microvias forming package interconnects. Ajinomoto supplies the film; substrate makers such as Unimicron and AT&S process materials into the finished substrate.

Entry sources reviewed: 2026-09-27

From film to substrate

Repeated lamination, microvia processing and circuit formation create multilayer signal and power connections. The finished substrate includes conductors and a core or other structures as well as ABF.

ABF substrates are one route within the broader IC-substrate category, not a name for every package substrate.

Manufacturing determines the usable capability

Fine routing, interlayer alignment, microvia reliability and warpage control require an integrated process.

The same film grade does not guarantee that different factories can produce substrates with identical specifications or yield.

Distinction: Film suppliers and substrate makers occupy different roles. A company list does not establish specific procurement relationships.

Company roles

Substrate makers use build-up dielectric materials to fabricate interconnect products; film manufacturers appear under ABF build-up insulating film.

Unimicron · Taiwan · Example role · ABF substrate manufacturing
Publicly documented ABF substrate production and yield-improvement work; supplies finished substrates.
Product / role source
Sources reviewed: 2026-09-27
Nan Ya PCB · Taiwan · Example role · IC substrate manufacturing
IC and ABF package substrates; a different role from supplying ABF insulating film.
Product / role source
Sources reviewed: 2026-09-27
AT&S · Austria · Example role · ABF substrate manufacturing
ABF substrates for high-performance processors.
Product / role source
Sources reviewed: 2026-09-27

Sources

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How the roles connect

Each connection appears once in this handbook. Classification describes a branch; technology links compare or relate approaches; service arrows point to the supported activity. Company examples do not establish a supply contract.

Connections, handoffs and sources
From / to	Handoff / relationship	Evidence
Printed Circuit Boards IC Package Substrates	Adjacent product stages Both use circuitry, insulation and microvias, but package substrates sit inside chip packages, not at the system-motherboard level.	IBIDEN \| IC package substrates, SAP and microvias 2026-09-26
Electronic Glass Cloth IC Package Substrates	Reinforcement in some organic cores Special glass fibers can control core expansion and stiffness; this differs from the role of ABF build-up layers.	Nittobo \| Electrical and thermomechanical requirements for specialty glass fiber 2026-09-26
IC Package Substrates CoWoS Advanced Packaging	Package support and connections The substrate supports CoWoS integration and connects to the system board; it differs from the interposer.	TSMC \| CoWoS-S/R/L 2026-09-26
High-Bandwidth Memory CoWoS Advanced Packaging	Integrated component CoWoS can integrate HBM and logic chips; HBM is memory, while CoWoS is packaging technology.	TSMC \| CoWoS-S/R/L 2026-09-26
CoWoS Advanced Packaging GPUs and AI Accelerators	Packaging-integration option Some high-performance GPUs and AI accelerators use this packaging; not all GPUs use CoWoS.	TSMC \| CoWoS-S/R/L 2026-09-26
High-Bandwidth Memory GPUs and AI Accelerators	High-bandwidth memory Some high-performance GPUs use HBM; capacity and bandwidth depend on configuration.	NVIDIA \| H200: a compute and HBM system example 2026-09-26
GPUs and AI Accelerators AI Servers	Computing component GPUs and accelerators combine with CPUs, memory, networking, power and cooling in AI systems.	NVIDIA \| DGX B200 hardware components 2026-09-26
EDA and Semiconductor IP IC Design	Design tools and IP EDA and reusable IP support chip design; they are not fabricated dies.	Synopsys \| Electronic design automation 2026-09-26
IC Design Wafer Fabrication	Design-process collaboration Designs must follow the selected process rules; this does not identify a specific outsourcing relationship.	TSMC \| Dedicated foundry roles 2026-09-26
Semiconductor Silicon Wafers Wafer Fabrication	Wafer substrate Material suppliers deliver substrates on which fabs form devices and interconnects; primarily silicon-based platforms here.	GlobalWafers \| Silicon-wafer products 2026-09-26
Process Chemicals and Gases Wafer Fabrication	Process materials Different steps require qualified chemicals, gases and precursors.	Tokyo Ohka Kogyo \| Semiconductor photoresists and chemicals 2026-09-26
Photomasks Lithography	Pattern-transfer tooling Masks carry patterns used with exposure systems and resist; platform and layer determine specifications.	Applied Materials \| Photomasks and pattern transfer 2026-09-26
Process Chemicals and Gases Lithography	Resist and supporting materials Resists and supporting chemicals serve coating, exposure, development and related steps.	Tokyo Ohka Kogyo \| Semiconductor photoresists and chemicals 2026-09-26
Lithography Wafer Fabrication	Pattern imaging A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	ASML \| Main steps in chip manufacturing 2026-09-26
Etching and Cleaning Wafer Fabrication	Material removal and cleaning A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	Lam Research \| Etching processes 2026-09-26
Thin-Film Deposition Wafer Fabrication	Thin-film formation A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	Lam Research \| Thin-film deposition 2026-09-26
Ion Implantation and Thermal Processing Wafer Fabrication	Doping and material modification A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	Applied Materials \| Ion implantation 2026-09-26
CMP Planarization Wafer Fabrication	Planarization A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	Applied Materials \| CMP planarization 2026-09-26
Metrology and Defect Inspection Wafer Fabrication	Process monitoring and feedback A wafer-manufacturing function repeated or interleaved by device and layer; not a fixed sequence or one supplier's complete process coverage.	KLA \| Introduction to chip manufacturing and process control 2026-09-26
Wafer Fabrication Semiconductor Packaging	Fabricated dies Testing, dicing and packaging depend on the product; wafer-level packaging can use a different sequence.	Amkor \| Semiconductor package types 2026-09-26
Wafer Fabrication Wafer and Packaged-Device Testing	Wafer probing Electrical tests can occur before packaging, not only afterward.	ASE \| Wafer probing, final test and system-level test 2026-09-26
Semiconductor Packaging Wafer and Packaged-Device Testing	Post-packaging testing Final and system-level tests verify product functions and specifications.	Amkor \| Wafer and package testing 2026-09-26
IC Package Substrates Semiconductor Packaging	Support and interconnect for selected packages Some packages use IC substrates; not every package requires an organic substrate.	Amkor \| Semiconductor package types 2026-09-26
Semiconductor Packaging CoWoS Advanced Packaging	One packaging-technology family CoWoS is TSMC's advanced-packaging family, not all chip packaging.	TSMC \| CoWoS-S/R/L 2026-09-26
IC Design GPUs and AI Accelerators	Chip-design role Connects design with a functional product; does not identify a particular chip's designer or foundry.	Synopsys \| Electronic design automation 2026-09-26
Semiconductor Packaging GPUs and AI Accelerators	Product-specific packaging Products use different packaging; not every GPU or SoC uses CoWoS.	Amkor \| Semiconductor package types 2026-09-26
IC Design SoCs and On-Device Computing	Chip-design role Connects design with a functional product; does not identify a particular chip's designer or foundry.	Synopsys \| Electronic design automation 2026-09-26
Semiconductor Packaging SoCs and On-Device Computing	Product-specific packaging Products use different packaging; not every GPU or SoC uses CoWoS.	Amkor \| Semiconductor package types 2026-09-26
Wafer Fabrication Memory and storage	Memory manufacturing DRAM and NAND have distinct processes; memory manufacturing does not establish logic-foundry capabilities.	Micron \| Memory products and manufacturing sites 2026-09-26
Wafer Fabrication High-Bandwidth Memory	DRAM dies and subsequent stacking HBM needs DRAM dies, vertical interconnects and stacking; wafer fabrication is one stage.	Micron \| HBM architecture 2026-09-26
ABF Build-up Film ABF Package Substrates	Build-up insulation Substrate makers process film into multilayer interconnects; a material-to-finished-product relationship.	Ajinomoto \| ABF build-up dielectric materials 2026-09-27
IC Package Substrates ABF Package Substrates	A type of package substrate ABF substrates are IC package substrates; the classification does not imply making a generic substrate first and then an ABF substrate.	Ajinomoto \| ABF build-up dielectric materials 2026-09-27
ABF Package Substrates Semiconductor Packaging	Package support and interconnects ABF substrates serve packages requiring this organic substrate type; not every package uses one.	Unimicron \| ABF substrates and quality management 2026-09-27
Wafer Fabrication Automotive Power and Control Semiconductors	Automotive semiconductor manufacturing entry Extends into the site's wafer-manufacturing chain; specific power devices require suitable materials, processes and automotive qualification, and not every fab makes them.	Infineon \| Automotive power semiconductors and electric-drive solutions 2026-09-30
ABF Build-up Film Glass Build-Up Layers and RDL Wiring	Optional: ABF build-up insulation Intel's public patent includes ABF on both sides of a glass core, showing coexistence is possible; it is not evidence of a particular mass-produced product or an Ajinomoto customer order.	Intel published patent US20260005081A1 \| Glass-core and ABF coexistence architecture 2026-09-30
IC Package Substrates Glass-Core Package Substrates	Substrates with glass cores One IC package-substrate architecture; not every substrate uses a glass core.	TOPPAN \| Glass-core FC-BGA and glass interposers 2026-09-30
Semiconductor Packaging Glass-Based Package Integration	Packaging with glass structures Connects to advanced packaging overall without classifying all existing assembly-and-test companies as GCS mass producers.	Intel \| ECTC 2026 glass-core, copper-filled TGV and packaging research 2026-09-30
Semiconductor Packaging CPO integration & packaging	Optical packaging services	NVIDIA \| 2026 platform manufacturing roles 2026-10-01
DRAM chips High-Bandwidth Memory	HBM is a DRAM architecture Scope note 1	Micron \| HBM products and architecture 2026-10-03
HBM logic base dies High-Bandwidth Memory	Logic base for the stack Scope note 1	SK hynix \| TSMC cooperation on HBM4 base dies and CoWoS integration 2026-10-03
HBM / PWF manufacturing High-Bandwidth Memory	Micron HBM manufacturing cooperation Scope note 1	PSMC \| March 16, 2026 Micron HBM/PWF cooperation 2026-10-03
Custom 3D memory integration GPUs and AI Accelerators	AI logic and memory integration Scope note 1	PSMC \| COMPUTEX 2026: 3D AI Foundry and ecosystem partners 2026-10-03
Memory assembly and test Wafer and Packaged-Device Testing	Memory-specific test services Scope note 1	PTI \| DRAM, NAND and NOR final test 2026-10-03
Memory wafer foundry Wafer Fabrication	Memory-specific wafer foundry Scope note 1	PSMC \| March 16, 2026 Micron HBM/PWF cooperation 2026-10-03
Inter-fab semiconductor logistics Wafer Fabrication	Wafer shipments and fab handoffs Scope note 2	Dimerco \| Global semiconductor transportation 2026-10-04
Inter-fab semiconductor logistics Semiconductor Packaging	Delivery to external assembly providers Scope note 2	Amkor \| Wafer bumping, probe, assembly and test 2026-10-04
Inter-fab semiconductor logistics Wafer and Packaged-Device Testing	Wafer or final-test handoffs Scope note 2	Amkor \| Wafer probe and wafer map management 2026-10-04
BT resin systems IC Package Substrates	Suitable BT grades for package substrates Scope note 3	MGC \| BT resin and laminates 2026-10-04
GPUs and AI Accelerators Compute trays and server modules	Processors and accelerator modules Scope note 4	NVIDIA \| MGX architecture and system partners 2026-10-05
IC Design Secure chips & NFC	Secure-chip application Connects IC design to payment chips without inferring manufacturing contracts.	NXP \| Secure payment chips and NFC 2026-10-06
Semiconductor Silicon Wafers Power-semiconductor epitaxy	Substrate route for Si epitaxy and GaN-on-Si Scope note 5	Episil-Precision \| GaN-on-Si epitaxial structures 2026-10-08
Semiconductor Packaging Power-device packaging and test	Power-device packaging branch Scope note 5	ASE \| Leadframe and power-device packaging 2026-10-08
Semiconductor Packaging IC and packaging scrap recovery	Scrapped ICs and components Scrapped ICs can enter material recovery by composition, distinct from repair and resale.	JYD \| Electronic scrap and metal recovery 2026-10-30
Wafer Fabrication Wafer reclaim	Eligible wafers sent for reclaim Suitable wafers are selected for stripping, polishing and cleaning.	PSI \| Wafer reclaim services 2026-10-30
Wafer reclaim Wafer Fabrication	Reclaimed wafer reuse Reuse depends on wafer and process requirements; arbitrary device-wafer use is not implied.	PSI \| Wafer reclaim services 2026-10-30
Semiconductor Silicon Wafers Silicon slurry recovery	Grinding and cutting by-products Based on the wafer grinding/cutting waste scope published by Semisils.	Semisils \| Silicon slurry and acid recovery 2026-10-30
Semiconductor Packaging Silicon slurry recovery	Dicing and grinding waste Wafer dicing/grinding slurry requires composition-specific acceptance and treatment.	Semisils \| Silicon slurry and acid recovery 2026-10-30
Wafer Fabrication Organic solvent recovery	Spent organic solvents Shangda discloses IC-manufacturing services, without naming a customer here.	Shangda \| Waste solvent purification 2026-10-30
Semiconductor Packaging Organic solvent recovery	Packaging and test solvents Shangda lists packaging/test customers by sector; treatment depends on stream type.	Shangda \| Waste solvent purification 2026-10-30
Wafer Fabrication TMAH developer recovery	Spent developer recovery A semiconductor waste source, not an undisclosed San Fu customer relationship.	San Fu Chemical \| TMAH recycling and subsidiary investment 2026-10-30
Wafer Fabrication Waste acid regeneration	Spent sulfuric acid treatment Semisils discloses semiconductor waste acid as feedstock; output is industrial grade.	Semisils \| Recovered industrial sulfuric acid 2026-10-30
Organic solvent recovery Process Chemicals and Gases	Return only when qualified TSMC solvent qualification example, not electronic-grade approval for all recyclers.	TSMC \| Chemical waste reuse (2026-01-12) 2026-10-30
TMAH developer recovery Process Chemicals and Gases	Regenerated developer chemicals San Fu discloses TMAH regeneration; actual adoption depends on customer qualification.	San Fu Chemical \| TMAH recycling and subsidiary investment 2026-10-30
Wafer Fabrication Metal-bearing wastewater recovery	Metal-bearing fab wastewater An applicable process source, not a contract with a company shown elsewhere.	WASTE Recovery Technology \| RecoCell electrowinning 2026-10-30
IC Design Client CPUs and SoCs	Chip design / manufacturing role Product function and industry roles; no company-to-company purchasing contract is asserted.	AMD \| Processors and graphics 2026-10-30
Wafer Fabrication Client CPUs and SoCs	Chip design / manufacturing role Product function and industry roles; no company-to-company purchasing contract is asserted.	AMD \| Processors and graphics 2026-10-30
Semiconductor Packaging Client CPUs and SoCs	Chip design / manufacturing role Product function and industry roles; no company-to-company purchasing contract is asserted.	AMD \| Processors and graphics 2026-10-30
GPUs and AI Accelerators Desktop personal computers	Optional graphics processing Product function and industry roles; no company-to-company purchasing contract is asserted.	AMD \| Processors and graphics 2026-10-30
GPUs and AI Accelerators Notebook computers	Model-dependent GPU configuration Product function and industry roles; no company-to-company purchasing contract is asserted.	AMD \| Processors and graphics 2026-10-30
GPUs and AI Accelerators Desktop graphics cards	Graphics chip integration Product function and industry roles; no company-to-company purchasing contract is asserted.	ASUS \| Graphics cards 2026-10-30
Semiconductor etch equipment Etching and Cleaning	Etch equipment support Equipment supports material removal, not every wet-cleaning application in the broader node.	Lam \| Etch processes and products 2026-10-30
Process Chemicals and Gases Etch gases and chemical materials	Etch-material branch Expands process materials into etch gases, not all wet chemicals.	Linde \| Electronic specialty gases 2026-10-30

Connection scope notes

a role relationship, not a contract among all listed companies.
describes a role relationship, not a specific company contract. The arrow points to the supported activity, not a one-way cargo route.
This is a representative feed, process or material relationship, not a vendor contract; not every reagent or operation is shown.
Functional or process relationship; not a contract among every company listed.
Material, component or system roles; not proof of supply contracts between all representative companies.

Why does a fabricated chip still need a separate packaging supply chain?

IC design, EDA and IP → Wafer fabrication

Processed wafers and test data → Die selection and packaging

Packaged components → Board-level systems

What changes the choice?

Explore the technologies and changes

FOWLP vs. FOPLP: Fan-Out Packaging Advantages, Production Bottlenecks, and Costs

Why AI Agents Drive CPU Demand: Workloads, Foundries, and the Named Supply Chain

HBM4 and HBM4E Technology and Supply Chains: How the Three Major Suppliers Combine Memory Processes and Advanced Packaging

The Semiconductor Cycle Through ASML, TSMC, and Micron Earnings: Where Is Demand Strong, and Which Recoveries Remain Unconfirmed?

Semiconductor supply chain

EDA and IP support different parts of design

Company roles

Sources

Design must fit the manufacturing process

Company roles

Sources

The connection back to boards

Capabilities can cross business categories

External assembly and wafer handoffs

Company roles

Sources

Electrical test and inspection answer different questions

Company roles

Sources

Wafer processes & materials

Material production precedes device fabrication

A material input to power semiconductors

Company roles

Sources

Fabrication is a repeated sequence

A fabricated wafer is not the final product

Company roles

Sources

Qualify capability for the platform

Company roles

Sources

Qualification follows the intended use

Company roles

Sources

Exposure works within a process sequence

Company roles

Sources

Identify the process location

Company roles

Sources

The structure determines the method

Company roles

Sources

Higher temperature is not inherently better

Company roles

Sources

Consumables and equipment have separate roles

Company roles

Sources

Process control differs from electrical testing

Company roles

Sources

Packaging & substrates

From film to substrate

Manufacturing determines the usable capability

Company roles

Sources

How the roles connect

Connection scope notes

Long-form guides (Chinese)

半導體產業鏈：從 IC 設計、晶圓製造到封裝測試

金融支付產業鏈：信用卡、行動支付與清算，誰做什麼、誰賺什麼？

運輸供應鏈：風力葉片、核燃料與晶片，如何送到下一家公司？